The present invention relates to the field of testing integrated circuits following fabrication. In particular, the present invention relates to a method and apparatus for testing image sensor circuits which is particularly well suited to the demands required of CMOS image sensor testers.
Semiconductor image sensing devices are finding widespread application with the increased use of digital still cameras and digital video cameras. Charge coupled device (CCD) technology has hitherto dominated the market for such imagers. A more recent emerging technology involves forming image sensors using complementary metaloxide silicon (CMOS) processing. CMOS image sensors are advantageous in that the CMOS process allows for the inclusion of circuits for image processing and the like, allowing a high level of product.integration to enable virtually all electronic camera functions to be integrated on a single chip. Image sensors manufactured in CMOS can also be made relatively inexpensively and facilitate significant power savings compared to CCD sensors, which are particularly important characteristics for portable consumer applications.
However, the additional functionality which can be integrated into a CMOS image sensor chip also increases the testing requirements of the product following fabrication. The testing of image sensors is more difficult than most integrated circuits because of the optical input required and because of the mixed analog and digital nature of the circuitry. These factors, together with the additional image processing functions and the like which can be included, make assessing CMOS image sensors the most demanding task for any mixed signal tester. In order to maintain the inexpensive price of CMOS image sensors, the testing procedures and apparatus must therefore be able to efficiently and accurately complete assessment of the functions of the fabricated circuits and chips at high speeds and in large volumes.
In accordance with the principles of the present invention, there is provided a testing apparatus and method for testing image sensing integrated circuits. The testing apparatus includes a test head adapted to receive an integrated circuit under test, and the test head has electrical contacts for making electrical connections to the integrated circuit, and a light source output arranged to shine test light on a light sensing portion of the integrated circuit whilst it is connected to the electrical contacts. The testing apparatus also includes controlling circuitry coupled to communicate with the integrated circuit by way of the electrical connections to control functions of the integrated circuit during testing. The testing apparatus further includes dedicated processing circuitry coupled through a fast data channel to the integrated circuit by way of the electrical connections to receive output signals from the integrated circuit during testing. The dedicated processing circuitry is adapted to analyze the output signals for the purpose of determining whether the integrated circuit under test meets predetermined test criteria.
In the preferred form of the invention, the controlling circuitry is coupled to communicate with the dedicated processing circuitry, wherein the controlling circuitry communicates testing parameters and pass/fail test limits to the processing circuitry and the processing circuitry communicates to the controlling circuitry indications of whether the integrated circuit under test passes or fails testing according to the output signal analysis. Preferably the test head includes mechanical apparatus for inserting and positioning the integrated circuit under test to make connection to said electrical contacts and for removing the integrated circuit following completion of testing. The removing operation of the mechanical apparatus can be controlled by the controlling circuitry according to the indications of whether the integrated circuit under test passes or fails testing.
In the preferred form of the invention, the fast data channel coupling the integrated circuit under test to the dedicated processing circuitry comprises a low-voltage differential signal (LVDS) transfer connection. The dedicated processing circuitry may comprise a computer equipped with one or more digital signal processor cards which are dedicated to the task of processing and analyzing the output signals from the integrated circuit under test.
In a preferred form of the invention, the testing apparatus includes a white light source and a light box, wherein the light source is coupled to transmit light through a first optic fiber to the light box, and the light box is coupled to transmit light through a second optic fiber to the light source output in the test head. The light box preferably incorporates an electronic filter disposed in the path of light passing from the first optic fiber to the second optic fiber to allow light from the white light source to be modified in a controlled fashion before reaching the light source output. The light box may also incorporate an electronically controlled shutter. The electronic filter may include a neutral density tunable liquid crystal attenuator and/or an electronic color sequence filter. Preferably the electronic filter and shutter are controlled by the tester. Preferably the light source output comprises an integrating sphere device for providing a flat field light output and a tapered coherent fused fiber optic bundle to direct the flat field light to shine on the light sensing portion of the integrated circuit.
According to one form of the invention, the test head includes a base portion having a seat for positioning the integrated circuit under test, with the light source output being mounted to the base portion and an aperture being provided to allow light from the light source output to shine on the integrated circuit light sensing portion when positioned in the seat. The base portion may further have electrical contact elements for coupling signals to the controlling circuitry and the dedicated processing circuitry. In this form of the invention the test head may also include a connecting portion which is moveable between open and closed positions relative to the base portion, the connecting portion having electrical input contacts which provide connections between the electrical contact elements of the base portion and contacts of the integrated circuit under test when positioned in the seat and with the connecting portion in its closed position.
The present invention also provides a method for testing image sensing integrated circuits. The method includes providing a test head having a seat for positioning an integrated circuit under test in relation to a light source output and for making electrical connections to said integrated circuit. The method also includes providing light from a light source through a first optic fiber to a light box having electronic filter and shutter control and from the light box through a second optic fiber to the light source output to shine on a light sensing portion of the integrated circuit when positioned in the seat of the test head. First control signals are provided from a tester to the integrated circuit by way of the test head to control the integrated circuit during testing, and second control signals are provided to the light box to control the electronic filter and shutter during testing. The method includes transferring output signals from the integrated circuit during testing to processing circuitry by way of a high speed data channel coupled between the test head and the processing circuitry, and analyzing the output signals in the processing circuitry to determine whether the integrated circuit passes or fails testing.
Preferably the controlling circuitry communicates testing parameters and pass/fail test limits to the processing circuitry and the processing circuitry communicates to the controlling circuitry indications of whether the integrated circuit under test passes or fails testing according to the output signal analysis. Preferably also, the high speed data channel by which output signals are transferred to dedicated processing circuitry comprises a low-voltage differential signal (LVDS) connection.
Preferably the test head includes mechanical apparatus for inserting and positioning the integrated circuit under test to make connection to said electrical contacts and for removing the integrated circuit following completion of testing, the method further including controlling the removing operation of the mechanical apparatus by the controlling circuitry according to the indications of whether the integrated circuit under test passes or fails testing.